Change symmetric cipher interface.
Change symmetric cipher interface so that multiple blocks could be submitted for en-/de-cryption at once. This would open the possibility to 1) use the VAES x86 instruction set, 2) interleave the currently proposed AES-NI instructions (AES is done in multiple rounds (up to 14) and each successive round depends on result of the previous one, but multiple blocks could be crypted in i-th round at the same time, if the CPU has more than one AES unit (they have), applicable to ECB, CTR, GCM modes and CBC, CFB decrypt modes).
Links:
- #23918 (comment)
- https://discord.com/channels/830522505605283862/843825120216743947/1258849619803242527
- https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
- https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_aesenc_epi128&ig_expand=232
- https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_aesenc_epi128&ig_expand=232,233
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